This invention relates generally to locking portions of addressable memory in a multiprocessor data processing system, and more particularly to a method and apparatus for controlling storage locks based on cache line ownership.
Data processing systems are becoming increasing complex. Some systems, such as Symmetric Multi-Processor (SMP) computer systems, couple two or more Instruction Processors (IPs) and multiple Input/Output (I/O) Modules to shared memory. This allows the multiple IPs to operate simultaneously on the same task, and also allows multiple tasks to be performed at the same time to increase system throughput.
As the number of units coupled to a shared memory increases, more demands are placed on the memory and memory latency increases. To address this problem, high-speed cache memory systems are often coupled to one or more of the processors for storing data signals that are copied from main memory. These cache memories are generally capable of processing requests faster than the main memory while also serving to reduce the number of requests that the main memory must handle, thereby increasing system throughput.
Although the use of cache memories enhances system throughput, it presents new design challenges. When multiple cache memories are coupled to a single main memory for the purpose of temporarily storing data signals, some system must be utilized to ensure that all processors are working from the same (most recent) copy of the data. For example, if a copy of a data item is stored and subsequently modified in a cache memory, another processor requesting access to the same data item must be prevented from using the older copy of the data item stored either in main memory or the requesting processor""s cache. This is referred to as maintaining cache xe2x80x9ccoherency.xe2x80x9d Maintaining cache coherency becomes more difficult as more cache memories are added to the system, because more copies of a single data item may require tracking.
There are various known methods for addressing this cache coherency quagmire. Some systems achieve coherency by implementing memory (storage) locks. That is, if an updated copy of data existed within a local cache, other processors were prohibited or xe2x80x9clocked outxe2x80x9d from obtaining a copy of the data from main memory, until the updated copy was returned to main memory which released the lock. More particularly, a storage xe2x80x9clockxe2x80x9d is a mechanism by which the exclusive use of a memory location is guaranteed by a requester. When a requester has a location xe2x80x9clocked,xe2x80x9d other requesters are denied access to the storage location until the first requester has completed its exclusive use operation, and has released the lock.
To initiate a storage lock, a requester may issue a specific command, or a command auxiliary to another command, that establishes the lock request (i.e., a storage lock instruction). The system generally waits for an indication that the lock is granted, and then allows the desired modification of the locked location using, for example, a write or store request. If the lock is not granted, the requester is precluded from making the requested modifications at that time, and must cancel, or most likely postpone, the request.
In one particular prior art system, storage locks are implemented using distributed lock CAMs (content addressable memory). The lock CAMs are implemented in a storage controller unit, and store addresses that are currently locked, or are waiting to be locked. Hardware lock logic within the storage controller unit uses the addresses in the CAM and compares them with any new lock requests, suspending (or rejecting) those new requests that are trying to access currently locked locations. For certain processor functions, the processor may require exclusive ownership of the data being processed due to the nature of the function being performed. Such processor functions may correspond to machine language macro-instructions such as the biased-fetch, test-and-set, increment-and-test, or conditional-replace instructions, which are instructions that accommodate the sharing of addressable memory. In order to ensure the exclusive ownership of data during processing of the instruction, the processor must lock the data from other devices in the computer.
However, in complex computing systems where, for example, each requester (e.g., processor) is associated with a different second level cache, yet shares third level cache and main memory with other requesters, a more efficient and effective system and method is needed to coordinate and guarantee exclusive control of data. Further, it would be desirable to utilize any generic memory or storage controller with a particular processing arrangement, without requiring the memory or storage unit to be equipped with hardware to accommodate the storage locking functions. The present invention provides a solution to this problem by providing a storage lock independent of the need for specific hardware in the storage or storage control, and therefore allows generic memory controllers to be used in the processing environment. The present invention therefore provides a solution to the aforementioned and other problems, and offers other advantages over the prior art.
The present invention relates to a system and method for controlling storage locks based on cache line ownership. The storage lock of the present invention is operable in connection with generic memory systems having no dedicated, hardware-implemented storage locks.
In accordance with one embodiment of the invention, a method is provided for controlling access to addressable, target data segments, to maintain memory coherency. Ownership of the target data segments is acquired at a memory targeted by a first requesting device, such as a processor. A storage lock is enabled that prohibits requesting devices, other than the first requesting device, from acting on the target data segments during the time the targeted memory xe2x80x9cownsxe2x80x9d the target data segments. A storage lock release signal is issued from the first requesting device to the targeted memory when exclusivity of the target data segments is no longer required at the first requesting device. In response, the storage lock at the targeted memory is released, thereby allowing other requesting devices to act on the target data segments.
In accordance with another embodiment of the invention, a system for maintaining cache coherency is provided. The system includes a main memory module for storing data, and a plurality of cache memory modules to cache portions of the data stored in the main memory module. A plurality of processing modules can each initiate commands requiring exclusive access to targeted cache lines stored in the cache memory module. A storage controller is configured to acquire ownership status of the cache lines targeted by a requesting processing module, and to enact a storage lock on the targeted cache lines while possessing ownership status of the targeted cache lines. The requesting processing module issues a storage lock release signal directing the storage controller to release the targeted cache lines when the requesting processing module has completed the operations requiring exclusivity of the targeted cache lines.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description. As will be realized, the invention is capable of other and different embodiments, and its details are capable of modification without departing from the scope and spirit of the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.